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description the m pd78001b(a)/78002b(a) are products in the m pd78002 subseries within the 78k/0 series. the m pd78001b(a)/78002b(a) have various peripheral hardware such as timer, serial interface and interrupt function. a one-time prom or eprom product, the m pd78p014, capable of operating in the same power supply voltage range as that of the mask rom product and other development tools is provided. functions are described in detail in the following user's manual, which should be read when carrying out design work. m pd78002, 78002y series user's manual: ieu-1334 features the m pd78001b, in comparison with the 78002b, is a higher reliability device, as a result of a more comprehensive quality assurance program (refer to quality grade on nec semiconductor devices (iei-1209)) large on-chip rom & ram mos integrated circuit m pd78001b(a), 78002b(a) 8-bit single-chip microcomputer the information in this document is subject to change without notice. 1995 data sheet item program memory data memory product name (rom) (internal high-speed ram) m pd78001b(a) 8k bytes 256 bytes 64-pin plastic shrink dip (750 mil) m pd78002b(a) 16k byte 384 bytes 64-pin plastic qfp ( 14 mm) package external memory expansion space: 64k bytes instruction execution time can be varied from high-speed (0.4 m s) to ultra-low-speed (122 m s) i/o ports: 53 (n-ch open-drain : 4) serial interface : 1 channel timer: 4 channels operating voltage range : 2.7 to 6.0 v application transmission equipment control device, gas detector circuit breaker, safety devices, etc. document no. ic-3599 (o.d. no. ic-9078) date published february 1995 p printed in japan
2 m pd78001b(a), 78002b(a) ordering information part number package quality grade m pd78001bcw (a)- 64-pin plastic shrink dip (750 mil) special m pd78001bgc (a)- -ab8 64-pin plastic qfp ( n n 14 mm) special m pd78002bcw (a)- 64-pin plastic shrink dip (750 mil) special m pd78002bgc (a)- -ab8 64-pin plastic qfp ( n n 14 mm) special remark indicates rom code no. please refer to "quality grade on nec semiconductor devices" (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. difference between the m pd78001b(a), 78002b(a) and the m pd78001b, 78002b. product name m pd78001b(a), 78002b(a) m pd78001b, 78002b item quality grade special standard
m pd78001b(a), 78002b(a) 3 78k/0 series product development these products are a further development in the 78k/0 series. the designations appearing inside the boxes are subseries names. products in volume production products under development y series products are compatible with i 2 c bus. 100-pin for control timer added to the pd78054, external interface functions 80-pin 64-pin low-voltage (1.8 v) operation version of the pd78014, with enhanced rom and ram variations a/d and 16-bit timer added to the pd78002 basic subseries for control 42/44-pin internal uart, low-voltage (1.8 v) operation possible for fip driving i/o, fip c/d of the pd78044a enhanced, display output total: 53 6-bit u/d counter added to the pd78024, display output total: 34 basic subseries for fip driving, display output total: 26 for lcd driving subseries for lcd driving, internal uart for iebus tm iebus controller added to the pd78054 pd78078 pd78054 pd78018f pd78014 pd78002 pd78083 pd78078y pd78054y pd78018fy pd78014y pd78002y pd780208 pd78044a pd78024 pd78064 pd78064y pd78098 64-pin 64-pin 100-pin 80-pin 64-pin 100-pin 78k/0 series 80-pin uart and d/a added to the pd78014, i/o enhanced m m m m m m m m m m m m m m m m m m mm m m m m the major functional differences among the subseries are shown below. function timer serial v dd external a/d d/a interface i/o min. expansion name 8-bit 16-bit watch watchdog value m pd78078 4ch 1ch 1ch 1ch 8-bit 8ch 8-bit 2ch 3ch (uart: 1ch) 88 1.8 v c m pd78054 2ch 69 2.0 v m pd78018f 2ch 53 1.8 v m pd78014 2.7 v m pd78002 1ch m pd78083 8-bit 8ch 1ch (uart: 1ch) 33 1.8 v m pd780208 2ch 1ch 1ch 1ch 8-bit 8ch 2ch 74 2.7 v m pd78044a 68 m pd78024 54 m pd78064 2ch 1ch 1ch 1ch 8-bit 8ch 2ch (uart: 1ch) 57 2.0 v m pd78098 2ch 1ch 1ch 1ch 8-bit 8ch 8-bit 2ch 3ch (uart: 1ch) 69 2.7 v c for control for lcd driving for iebus tm for fip ? driving
4 m pd78001b(a), 78002b(a) overview of function item rom internal high- speed ram 8k bytes 16k bytes 64k bytes 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip instruction execution time cycle modification function 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz operation) 122 m s (at 32.768 khz operation) ? 16-bit operation ? bit manipulation (set, reset, test, boolean operation) ? bcd correction, etc. total : 53 ? cmos input : 0 2 ? cmos i/o : 47 ? n-channel open-drain i/o (15 v withstand voltage) : 0 4 ? 3-wire/sbi/2-wire mode selectable ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 2 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (at main system clock 10.0 mhz operation), 32.768 khz (at subsystem clock 32.768 khz operation) 2.4 khz, 4.9 khz, 9.8 khz (at main system clock 10.0 mhz operation) internal : 5 external : 4 internal : 1 internal : 1 internal : 1 external : 1 v dd = 2.7 to 6.0 v C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp ( n n 14 mm) 256 bytes 384 bytes when main system clock selected when subsystem clock selected maskable interrupts non-maskable interrupt software interrupt product name m pd78001b(a) m pd78002b(a) internal memory memory space general registers instruction cycle instruction set i/o ports serial interface timer timer output clock output buzzer output vectored interrupts test input operating voltage range operating ambient temperature range package
m pd78001b(a), 78002b(a) 5 1. pin configuration (top view) .............................................................................................. ....... 6 2. block diagram ............................................................................................................... .................... 9 3. pin functions ............................................................................................................... ...................... 10 3.1 port pins .................................................................................................................. .................................... 10 3.2 other pins ................................................................................................................. .................................. 12 3.3 pin i/o circuit and recommended connection of unused pins ...................................... 13 4. memory space ................................................................................................................ .................... 15 5. peripheral hardware function features ............................................................................ 16 5.1 ports ....................................................................................................................... ....................................... 16 5.2 clock generator ............................................................................................................ .......................... 17 5.3 timer/event counter ........................................................................................................ ...................... 18 5.4 clock output control circuit ............................................................................................. ............ 20 5.5 buzzer output control circuit ............................................................................................ ........... 20 5.6 serial interfaces .......................................................................................................... ........................... 21 6. interrupt functions and test functions .......................................................................... 22 6.1 interrupt functions ........................................................................................................ ....................... 22 6.2 test functions ............................................................................................................. ............................. 25 7. external device expansion functions ................................................................................. 26 8. standby functions ........................................................................................................... .............. 26 9. reset function .............................................................................................................. .................... 26 10. instruction set ............................................................................................................ .................... 27 11. electrical specifications .................................................................................................. ........... 30 12. characteristic curve (reference values) ........................................................................... 48 13. package drawings ........................................................................................................... ................ 52 14. recommended soldering conditions ..................................................................................... 56 appendix a. development tools ............................................................................................... ....... 57 appendix b. related documents ............................................................................................... ....... 59 contents
6 m pd78001b(a), 78002b(a) 1 p20 2 p21 3 p22 4 p23 5 p24 6 p25/si0/sb0 7 p26/so0/sb1 8 p27/sck0 9 p30 10 p31/to1 11 p32/to2 12 p33/ti1 13 p34/ti2 14 p35/pcl 15 p36/buz 16 p37 17 v ss 18 p40/ad0 19 p41/ad1 20 p42/ad2 21 p43/ad3 22 p44/ad4 23 p45/ad5 24 p46/ad6 25 p47/ad7 26 p50/a8 27 p51/a9 28 p52/a10 29 p53/a11 30 p54/a12 31 p55/a13 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ic3 ic2 p17 p16 p15 p14 p13 p12 p11 p10 ic1 p04/xt1 xt2 ic0 x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0 reset p67/astb p66/wait p65/wr p64/rd p63 p62 p61 p60 p57/a15 p56/a14 1. pin configuration (top view) 64-pin plastic shrink dip (750 mil) remark always connect the ic0, ic1 and ic3 (internally connected) pins to v ss directly. always connect the ic2 pin to v dd directly. m pd78001bcw(a)C m pd78002bcw(a)C
m pd78001b(a), 78002b(a) 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p11 p10 ic1 p04/xt1 xt2 ic0 x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0 reset p67/astb p66/wait p37 v ss p30 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/sck0 p26/so0/sb1 p25/si0/sb0 p24 p23 p22 p21 p20 ic3 ic2 p17 p16 p15 p14 p13 p12 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd p65/wr m pd78001bgc(a)C Cab8 m pd78002bgc(a)C Cab8 remark always connect the ic0, ic1 and ic3 (internally connected) pins to v ss directly. always connect the ic2 pin to v dd directly. 64-pin plastic qfp ( n n 14 mm)
8 m pd78001b(a), 78002b(a) p00 to p04 : port 0 p10 to p17 : port 1 p20 to p27 : port 2 p30 to p37 : port 3 p40 to p47 : port 4 p50 to p57 : port 5 p60 to p67 : port 6 intp0 to intp3 : interrupt from peripherals ti1, ti2 : timer input to1, to2 : timer output sb0, sb1 : serial bus si0 : serial input so0 : serial output sck0 : serial clock pcl : programmable clock buz : buzzer clock ad0 to ad7 : address/data bus a8 to a15 : address bus rd : read strobe wr : write strobe wait : wait astb : address strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) reset : reset v dd : power supply v ss : ground ic0 to ic3 : internally connected
9 m pd78001b(a), 78002b(a) 2. block diagram p01-p03 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 port0 port1 port2 port3 port4 port5 port6 external access 78k/0 cpu core 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer watch timer serial interface 0 interrupt control to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 intp0/p00 ? intp3/p03 p00 p04 rom ram buzzer output buz/p36 clock output control pcl/p35 reset x1 x2 xt1/p04 xt2 system control v dd v ss ic0- ic3 remark internal rom & ram capacity varies depending on the product.
10 m pd78001b(a), 78002b(a) 3. pin functions 3.1 port pins (1/2) intp0 intp1 intp2 intp3 xt1 C C C C C C si0/sb0 so0/sb1 sck0 C to1 to2 ti1 ti2 pcl buz C ad0 to ad7 p00 p01 p02 p03 p04 * p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 port 0 5-bit i/o port input only input input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. input only input/ output input/ output port 3 8-bit input/output port. input/output can be specified in bit-wise. when used as an input port, pull-up resistor can be used by software. input/ output input/ output input/ output input port 4 8-bit input/output port. input/output can be specified in 8-bit unit. when used as an input port, pull-up resistor can be used by software. test input flag (krif) is set to 1 by falling edge detection. port 2 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. port 1 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. input input input input input input pin name i/o function dual- function pin after reset * when using the p04/xt1 pins as an input port, set 1 to bit 6 (frc) of the processor control register. (do not use the on-chip feedback register of the subsystem clock oscillator.)
11 m pd78001b(a), 78002b(a) a8 to a15 rd wr wait astb input/ output port 5 8-bit input/output port. led can be driven directly. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. p50 to p57 p60 p61 p62 p63 p64 p65 p66 p67 input/ output port 6 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. n-ch open-drain input/output port. on- chip pull-up resistor can be specified by mask option. led can be driven directly. pin name i/o function after reset 3.1 port pins (2/2) dual- function pin input input caution when pull-up resistors are not used (specified by mask option), the low-level input leak current increases with -200 m a (max.) under either of the following conditions. 1 when the external device expansion function is used and a low-level is input to the pin. 2 during the 3-clock period when a read instruction is executed on port 6 (p6) and the port mode register (pm6).
12 m pd78001b(a), 78002b(a) intp0 input effective edge (rising edge, falling edge, or both rising edge and falling edge) input p00 intp1 can be specified. p01 intp2 external interrupt input. p02 intp3 falling edge detection external interrupt input. p03 si0 input serial interface serial data input. input p25/sb0 so0 output serial interface serial data output. input p26/sb1 sb0 input serial interface serial data input/output. input p25/si0 sb1 /output p26/so0 sck0 input serial interface serial clock input/output. input p27 /output ti1 input external count clock input to 8-bit timer (tm1). input p33 ti2 external count clock input to 8-bit timer (tm2). p34 to1 output 8-bit timer (tm1) output. input p31 to2 8-bit timer (tm2) output. p32 pcl output clock output (for main system clock, subsystem clock trimming). input p35 buz output buzzer output. input p36 ad0 to ad7 input low-order address/data bus at external memory expansion. input p40 to p47 /output a8 to a15 output high-order address bus at external memory expansion. input p50 to p57 rd output external memory read operation strobe signal output. input p64 wr external memory write operation strobe signal output. p65 wait input wait insertion at external memory access. input p66 astb output strobe output which latches the address information output at port 4 and input p67 port 5 to access external memory. reset input system reset input. x1 input main system clock oscillation crystal connection. x2 xt1 input subsystem clock oscillation crystal connection. input p04 xt2 v dd positive power supply. v ss ground potential. ic0 to ic3 internal connection. ic0/ic1/ic3 and ic2 should be connected directly to v ss v dd , respecitively. after reset dual- function pin 3.2 other pins function pin name i/o
13 m pd78001b(a), 78002b(a) 2 8-a 16 5-a 10-a 5-a 8-a 5-a 5-e 5-a 13-b 5-a 2 16 p00/intp0 p01/intp1 p02/intp2 p03/intp3 p04/xt1 p10 to p17 p20 to p24 p25/si0/sb0 p26/so0/sb1 p27/sck0 p30 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60 to p63 p64/rd p65/wr p66/wait p67/astb reset xt2 ic0, ic1, ic3 ic2 input/output circuit type 3.3 pin i/o circuit and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, see fig. 3-1. table 3-1 input/output circuit type of each pin recommended connection when not used i/o pin name input input/output input input/output input leave open. connected to v ss directly. connected to v dd directly. connected to v ss . connected to v ss through resistor independently. connected to v dd or v ss . connected to v dd or v ss through resistor independently. connected to v dd through resistor independently. connected to v dd or v ss through resistor independently. connected to v dd through resistor independently. connected to v dd or v ss through resistor independently.
14 m pd78001b(a), 78002b(a) pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd open drain xt1 data output disable n-ch in / out v dd v dd rd mask option middle-high voltage input buffer feedback cut-off xt2 p-ch p-ch fig. 3-1 pin input/output circuits type 2 type 5-a type 5-e type 8-a type 10-a type 13-b type 16 pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd input enable pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd in schmitt-triggered input with hysteresis characteristic
m pd78001b(a), 78002b(a) 15 4. memory space the memory map of m pd78001b(a)/78002b(a) is shown in fig. 4-1. fig. 4-1 memory map remark shaded area indicates internal memory. * intermal rom and internal high-speed ram capacities vary depending on the product (see the table below). internal rom end address nnnnh 1fffh 3fffh product name m pd78001b(a) m pd78002b(a) internal high-speed ram start address mmmmh fe00h fd80h ffffh ff00h feffh mmmmh mmmmh? fee0h fedfh fa80h fa7fh nnnnh+1 nnnnh 0000h nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h use prohibited external memory program area callf entry area program area callt table area vector table area program memory space data memory space special function registers (sfr) 256 8 bits internal high-speed ram * general registers 32 8 bits internal rom *
16 m pd78001b(a), 78002b(a) caution when pull-up resistors are not used (specified by mask option), low-level input leak current increases with C200 m a (max.) under either of the following conditions. 1 when the external device expansion function is used and a low-level is input to the pin. 2 during the 3-clock period when a read instruction is executed on port 6 (p6) and the port mode register (pm6). port 0 port 1 port 2 port 3 port 4 port 5 port 6 p00, p04 p01 to p03 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p63 p64 to p67 5 peripheral hardware function features 5.1 ports the i/o port has the following three types. ? cmos input (p00, p04) : 2 ? cmos input/output (p01 to p03, port 1 to port 5, p64 to p67) : 47 ? n-ch open-drain input/output (15v withstand voltage) (p60 to p63) : 4 total : 53 table 5-1 functions of ports port name dedicated input port input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. input/output ports. input/output can be specified in 8-bit units. when used as an input port, pull-up resistor can be used by software. test input flag (krif) is set to 1 by falling edge detection. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. led can be driven directly. n-ch open-drain input/output port. input/output can be specified bit-wise. on-chip pull-up resistor can be specified by mask option. led can be driven directly. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used by software. pin name function
m pd78001b(a), 78002b(a) 17 5.2 clock generator there are two types of clock generator: main system clock and subsystem clock. the instruction exection time can be changed. ? 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (mainsystem clock: at 10.0 mhz operation) ? 122 m s (subsystem clock: at 32.768 khz operation) fig. 5-1 clock generator block diagram xt1/p04 xt2 x1 x2 f x f xt stop f x 2 f x 2 2 f x 2 3 f x 2 4 subsystem clock osicillator main system clock osicillator prescaler prescaler selector standby control circuit wait control circuit intp0 sampling clock cpu clock (f cpu ) clock to peripheral hardware watch timer clock output function
18 m pd78001b(a), 78002b(a) 5.3 timer/event counter the following four channels are incorporated in the timer/event counter. ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel table 5-2 types and features of timer/event counter fig. 5-2 8-bit timer/enent counter block diagram type interval timer 2 channels 1 channel 1 channel external event counter 2 channels C C functions timer output 2 outputs C C sqare wave output 2 outputs C C interrupt request 2 2 1 8-bit timer/event counter watch timer watchdog timer internal bus 8-bit compare register (cr10) 8-bit timer register 1 (tm1) clear output control circuit output control circuit inttm1 to2/p32 inttm2 to1/p31 clear match selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) internal bus selector selector match f x /2 ?f x /2 10 f x /2 12 ti1/p33 f x /2 ?f x /2 10 f x /2 12 ti1/p34 selector selector
m pd78001b(a), 78002b(a) 19 fig. 5-3 watch timer block diagram fig. 5-4 watchdog timer block diagram inttm3 intwt 5-bit counter prescaler selector selector f xt 8 f x /2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f w 2 f w 14 f w 2 13 f w 2 selector selector control circuit 8-bit counter prescaler intwdt non-maskable interrupt request intwdt maskable interrupt request reset selector 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f w 2 10 f w 2 12 f w 2
20 m pd78001b(a), 78002b(a) 5.4 clock output control circuit the clock with the following frequencies can be output for clock output. ? 39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz (main system clock: at 10.0 mhz operation) ? 32.768 khz (subsystem clock: at 32.768 khz operation) fig. 5-5 clock output control block diagram 5.5 buzzer output control circuit the clock with the following frequencies can be output for buzzer output. ? 2.4 khz/4.9 khz/9.8 khz (main system clock: at 10.0 mhz operation) fig. 5-6 buzzer output control block diagram selector synchronization circuit output control circuit pcl/p35 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f xt selector output control circuit buz/p36 f x /2 10 f x /2 11 f x /2 12
m pd78001b(a), 78002b(a) 21 5.6 serial interfaces there is one on-chip clocked serial interface. serial interface channel 0 has the following three modes. ? 3-wire serial i/o mode : msb/lsb-first switchable ? sbi (serial bus interface) mode : msb-first ? 2-wire serial i/o mode : msb-first fig. 5-7 serial interface channel 0 block diagram busy/acknowledge output circuit output latch serial i/o shift register 0 (sio0) internal bus interrupt request signal generator serial counter bus release/command/ acknowledge detection circuit serial clock control circuit selector selector selector f x /2 ?f x /2 29 to2 intcsi0 sck0/p27 so0/sb1/p26 si0/sb0/p25
22 m pd78001b(a), 78002b(a) internal external internal internal intwdt intwdt intp0 intp1 intp2 intp3 intcsi0 inttm3 inttm1 inttm2 brk 0004h 0006h 0008h 000ah 000ch 000eh 0012h 0016h 0018h 003eh interrupt source non- maskable maskable software name trigger watchdog timer overflow (with non- maskable interrupt selected) watchdog timer overflow (with interval timer selected) pin input edge detection serial interface channel 0 transfer end reference time interval signal from watch timer 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation brk instruction execution internal/ external vector table adress basic configuration type *2 default priority *1 interrupt type *1. the default priority is the priority applicable when more priority than one maskable interrupt is generated. 0 is the highest and 11, the lowest. 2. basic configuration types a to e correspond to (a) to (e) on the next page. 6. interrupt functions and dest functions 6.1 interrupt functions there are 11 interrupt functions of 3 different kinds as shown below. ? non-maskable interrupt : 1 ? maskable interrupt : 9 ? software interrupt : 1 table 6-1 interrrupt source list a b c d b e 0 1 2 3 4 5 6 7 8
m pd78001b(a), 78002b(a) 23 mk ie pr isp if priority control circuit vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) edge detector sampling clock internal bus standby release signal interrupt request (b) internal maskable interrupt (c) external maskable interrupt (intp0) fig. 6-1 interrupt function basic configuration (1/2) (a) internal non-maskable interrupt internal bus priority control circuit vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority control circuit vector table address generator standby release signal interrupt request
24 m pd78001b(a), 78002b(a) fig. 6-1 interrupt function basic configuration (2/2) (d) external maskable interrupt (except intp0) (e) software interrupt remarks 1. if : interrupt request flag 2. ie : interrupt enable flag 3. isp : in-service priority flag 4. mk : interrupt mask flag 5. pr : priority spcification flag mk ie pr isp if priority control circuit vector table address generator external interrupt mode register (intm0) edge detector internal bus standby release signal interrupt request priority control circuit vector table address generator internal bus interrupt request
m pd78001b(a), 78002b(a) 25 6.2 test functions there are two test functions as shown in table 6-2. table 6-2 test source list test source name trigger intwt watch timer overflow internal ntpt4 port 4 falling edge detection external internal/external mk internal bus if standby release signal test input remarks 1. if : test input flag 2. mk : test mask flag fig. 6-2 test function basic configuration
26 m pd78001b(a), 78002b(a) 7. external device expansion functions the external device expansion function is used to connect external devices to areas other than the internal rom, ram and sfr. ports 4 to 6 are used for connection with external devices. 8. standby functions there are the following two standby functions to reduce the current dissipation. ? halt mode : the cpu operating clock is stopped. the average consumption current can be reduced by intermittent operation in combination with the normal operating mode. ? stop mode : the main system clock oscillation is stopped. the whole operation by the main system clock is stopped, so that the system operates with ultra-low power consumption using only the sub- system clock. fig. 8-1 standby functions * the power consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set the mcc to stop the main system clock. the stop instruction cannot be used. caution when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program by the program. 9. reset function there are the following two reset methods. ? external reset input by reset pin. ? internal reset by watchdog timer runaway time detection. main system clock operation stop mode (main system clock oscillation stopped) halt mode (clock supply to cpu is stopped, oscillation) subsystem clock operation * halt mode * (clock supply to cpu is stopped, oscillation) interrupt request interrupt request interrupt request halt instruction halt instruction stop instruction css=1 css=0
m pd78001b(a), 78002b(a) 27 10. instruction set (1) 8-bit instruction mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz [hl+byte] #byte a r * sfr saddr !addr16 psw [de] [hl] [hl+b] $addr16 1 none [hl+c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp r1 dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl+byte] mov [hl+b] [hl+c] 2nd operand 1st operand * except r = a
28 m pd78001b(a), 78002b(a) a.bit sfr.bit saddr.bit pws.bit [hl].bit cy $addr16 none a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 (2) 16-bit instruction movw, xchw addw, subw, cmpw, push, pop, incw, decw (3) bit operation instruction mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr #word ax rp * sfrp saddrp !addr16 sp none ax addw movw movw movw movw movw subw xchw cmpw rp movw movw * incw, decw push, pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw * only when rp = bc, de, hl. 1st operand 2nd operand 2nd operand 1st operand
m pd78001b(a), 78002b(a) 29 (4) call instruction/branch instruction call, callf, callt, br, bc, bnc, bz, bnz, bt, bf,btclr, dbnz ax !addr16 !addr11 [addr5] $addr16 basic instruction br call, br callf callt br, bc, bnc, bz, bnz compound instruction bt, bf, btclr, dbnz (5) other instruction adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 2nd operand 1st operand
30 m pd78001b(a), 78002b(a) parameter symbol test conditions rating unit supply voltage v dd C0.3 to + 7.0 v input voltage v i1 p00 to p04, p10 to p17, p20 to p27, p30 top37 C0.3 to v dd + 0.3 v p40 to p47, p50 to p57, p64 to p67, x1, x2, xt2 v i2 p60 to p67 open-drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v output 1 pin C10 ma current high i oh p10 to p17, p20 to p27, p30 to p37 total C15 ma p01 to p03, p40 to p47, p50 to p57, p60 to p67 total C15 ma output 1 pin peak value 30 ma current low effective value 15 ma p40 to p47, p50 to p55 total peak value 100 ma effective value 70 ma i ol * p01 to p03, p56, p57, peak value 100 ma p60 to p67 total effective value 70 ma p01 to p03, peak value 50 ma p64 to p67 total effective value 20 ma p10 to p17, p20 to p27, p30 to p37 peak value 50 ma total effective value 20 ma operating ambient t a C40 to +85 c temperature storage t stg C65 to +150 c temperature 11. electrical specifications absolute maximum ratings (t a = 25 c) * effective value should be calculated as follows: [effective value] = [peak value] ? duty caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. that is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
m pd78001b(a), 78002b(a) 31 parameter symbol test conditions min. typ. max. unit input capacitance c in f=1 mhz unmeasured pins returned to 0 v 15 pf i/o capacitance p01 to p03, p10 to p17, p20 to p27, p30 to p37, 15 pf c io p40 top47, p50 to p57, p64 to p67 p60 to p63 20 pf capacitance (t a = 25 c, v dd = v ss = 0 v) f=1 mhz unmeasured pins returned to 0 v remark the characteristics of a dual-function pin and a port pin are the same unless specified otherwise. main system clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter oscillator frequency (f x ) *1 oscillation stabilization time *2 oscillator frequency (f x ) *1 oscillation stabilization time *2 x1 input frequency (f x ) *1 x1 input high/low level width (t xh , t xl ) unit mhz ms mhz ms mhz ns resonator ceramic resonator crystal resonator external clock recommended circuit test conditions v dd = oscillator voltage range after v dd reaches oscil- lator voltage range min. v dd = 4.5 to 6.0 v min. 1 1 1.0 42.5 typ. 8.38 max. 10 4 10 10 30 10.0 500 m pd74hcu04 *1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wiring the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as vss. ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. x1 x2 c2 c1 r1 v ss x1 x2 c2 c1 v ss x1 x2
32 m pd78001b(a), 78002b(a) subsystem clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) unit khz s khz m s max. 35 2 10 100 15 test conditions v dd = 4.5 to 6.0 v parameter oscillator frequency (f xt ) *1 oscillation stabilization time *2 xt1 input frequency (f xt ) *1 xt1 input high/low level width (t xth , t xtl ) resonator crystal resonator external clock recommended circuit xt1 xt2 xt1 xt2 c4 c3 r2 v ss min. 32 32 5 typ. 32.768 1.2 *1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillator voltage min. c autions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as vss. ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. the subsystem clock oscillation circuit is a circuit with a low amplification level, more prone to misoperation due to noise than the main system clock. when using the subsystem clock, special care is needed regarding the wiring method.
m pd78001b(a), 78002b(a) 33 100 100 100 100 on-chip 30 on-chip 30 on-chip 30 on-chip C 33 33 100 recommended oscillation constant oscillation voltage range c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) recommended oscillation circuit constant main system clock ceramic resonator (t a = C40 to +85 c) manufacturer products frequency (mhz) murata m.f.g. kyocera csb1000j csb j csa . mk csa . mg cst . mg csa . mg cst . mgw csa . mg cst . mgw csa . mt cst . mtw kbr-4.19mws kbr-4.19mks kbr-4.19msa pbrc4.19a kbr-10.0m kbr-1000f kbr-1000y 1.00 1.01-1.25 1.26-1.79 1.80-2.44 2.45-4.18 4.19-6.00 6.01-10.0 4.19 4.19 10.0 1.00 6.8 4.7 0 0 0 0 0 0 0 0 0 C C C 2.2 2.9 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.9 2.9 2.7 2.7 2.8 2.7 100 100 100 100 on-chip 30 on-chip 30 on-chip 30 on-chip C 33 33 100 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 remark , . , . indicates frequency. recommended circuit constant oscillation voltage range c3 (pf) c4 (pf) r2 (k w ) min. (v) max. (v) manufacturer products frequency (mhz) daishinku corp. dt-38 (1ta632e00, load capacitance 6.3pf) 32.768 8 100 2.7 6.0 8 subsystem clock: crystal resonator (t a = C40 to +60 c) caution regarding the oscillator circuit constant, operation is guaranteed, but reliability is not guaranteed. customers who require high reliability should directly consult the resonator manufacturer.
34 m pd78001b(a), 78002b(a) dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit input voltage v ih1 p10 to p17, p21, p23, p30 to p32, p35 to p37, 0.7 v dd v dd v high p40 to p47, p50 to p57, p64 to p67 v ih2 p00 to p03, p20, p22, p24 to p27, p33, p34, reset 0.8 v dd v dd v v ih3 p60 to p63 open-drain 0.7 v dd 15 v v ih4 x1, x2 v dd -0.5 v dd v v ih5 xt1/p04, xt2 v dd = 4.5 to 6.0 v v dd -0.5 v dd v v dd -0.3 v dd v input voltage v il1 p10 to p17, p21, p23, p30 to p32, p35 to p37 0 0.3 v dd v low p40 to p47, p50 to p57, p64 to p67 v il2 p00 to p03, p20, p22, p24 to p27, p33, p34, reset 0 0.2 v dd v v il3 p60 to p63 v dd = 4.5 to 6.0 v 0 0.3 v dd v 0 0.2 v dd v v il4 x1, x2 0 0.4 v v il5 xt1/p04, xt2 v dd = 4.5 to 6.0 v 0 0.4 v 0 0.3 v output voltage v oh1 v dd = 4.5 to 6.0 v,i oh = C1 ma v dd -1.0 v high i oh = C100 m a v dd -0.5 v output voltage p50 to p57, p60 to p63 v dd = 4.5 to 6.0 v, 0.4 2.0 v low v ol1 i ol = 15 ma p01 to p03, p10 to p17, p20 to p27, v dd = 4.5 to 6.0 v, 0.4 v p30 to p37, p40 to p47, p64 to p67 i ol = 1.6 ma v dd = 4.5 to 6.0 v, v ol2 sb0, sb1, sck0 open-drain 0.2 v dd v pulled-up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v input leakage p00 to p03, p10 to p17, current high i lih1 p20 to p27, p30 to p37, 3 m a v in = v dd p40 to p47, p50 to p57, p60 to p67, reset i lih2 x1, x2, xt1/p04, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a input leakage p00 to p03, p10 to p17, current high i lil1 p20 to p27, p30 to p37, C3 m a p40 to p47, p50 to p57, v in = 0 v p64 to p67, reset i lil2 x1, x2, xt1/p04, xt2 C20 m a i lil3 p60 to *1 C200 m a p63 other than above C3 *2 m a *1. when memory expansion mode is used by the memory expansion mode register (mm) with no on-chip pull-up resistor by mask option. 2. when pull-up resistors are not used (specified by mask option), the low-level input leakage current increases with C200 m a (max.) under either of the following conditions. q when the external device expansion function is used and a low level is input to the pin. w during the 3-clock period when a read instruction is executed on port 6 (p6) and the port mode registor (pm6). remark the characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
m pd78001b(a), 78002b(a) 35 parameter symbol test conditions min. typ. max. unit output leakage i loh1 v out = vdd 3 m a current high output leakage i lol v out = 0 v C3 m a current low mask option pull- r 1 v in = 0 v, p60 to p63 20 40 90 k w up resister software pull- v in = 0 v, p01 to p03, 4.5 v v dd < 6.0 v 15 40 90 k w up resister r 2 p10 to p17, p20 to p27, p30 to p37, p40 to p47, 2.7 v v dd < 4.5 v 20 500 k w p50 to p57, p64 to p67 i dd1 v dd = 5.0 v 10 % *1 7.5 22.5 ma v dd = 3.0 v 10 % *2 0.8 2.4 ma i dd2 v dd = 5.0 v 10 % 1.4 4.2 m a v dd = 3.0 v 10 % 550 1650 m a i dd3 v dd = 5.0 v 10 % 60 120 m a v dd = 3.0 v 10 % 35 70 m a i dd4 v dd = 5.0 v 10 % 25 50 m a v dd = 3.0 v 10 % 5 10 m a i dd5 v dd = 5.0 v 10 % 1 20 m a v dd = 3.0 v 10 % 0.5 10 m a i dd6 v dd = 5.0 v 10 % 0.1 20 m a v dd = 3.0 v 10 % 0.05 10 m a dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) power supply current *3 *1. operating in high-speed mode (when set the processor clock control register to 00h). 2. operating in low-speed mode (when set the processor clock control register to 04h). 3. port current are excluded. remark the characteristics of a dual-function pin and a port pin are the same unless specified otherwise. 8.38 mhz crystal oscillation operating mode 8.38 mhz crystal oscillation halt mode 32.768 khz crystal oscillation operating mode 32.768 khz crystal oscillation halt mode xt1 = 0 v stop mode when feedback resister is used xt1 = 0 v stop mode when feedback resister is unused
36 m pd78001b(a), 78002b(a) ac characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) (1) basic operation m pd78001b(a), 78002b(a) t cy vs v dd (at main system clock operation) m pd78p014 (reference) t cy vs v dd (at main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range caution the operation guaranteed range of the m pd78001b(a), and 78002b(a) differs from that of the m pd78p014. parameter symbol test conditions min. typ. max. unit cycle time operating on main v dd = 4.5 to 6.0 v 0.4 64 m s (min. instruction t cy system clock 0.96 64 m s execution time) operationg on subsystem clock 40 122 125 m s ti input f ti v dd = 4.5 to 6.0 v 0 4 mhz frequency 0 275 khz ti input high/ t tih v dd = 4.5 to 6.0 v 100 ns low-level width t til 1.8 m s interrupt input t inth intp0 8/f sam * m s high/low-level t intl intp1 to intp3 10 m s width kr0 to kr7 10 m s reset low t rsl 10 m s level width * in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register, selection of fsam is possible between fx/2 n+1 , f x /64 and f x /128 (when n = 0 to 4). cycle time t cy [ m s] cycle time t cy [ m s] remark indicates t a =C40 to +40 c indicates t a =C40 to +85 c
m pd78001b(a), 78002b(a) 37 parameter symbol test conditions min. max. unit astb high-level width t asth 0.5t cy ns address setup time t ads 0.5t cy C30 ns address hold time t adh load resistor 3 5 k w 10 ns data input time from address t add1 (2+2n)t cy C50 ns t add2 5 (3+2n)t cy C100 ns data input time from rd t rdd1 (1+2n)t cy C25 ns t rdd2 (2.5+2n)t cy C100 ns read data hold time t rdh 0 ns rd low-level width t rdl1 (1.5+2n)t cy C20 ns t rdl2 (2.5+2n)t cy C20 ns wait input time from rd t rdwt1 0.5t cy ns t rdwt2 1.5t cy ns wait input time from wr t wrwt 0.5t cy ns wait low-level width t wtl (0.5+2n)t cy +10 (2+2n)t cy ns write data setup time t wds 100 ns write data hold time t wdh 5 ns wr low-level width t wrl1 (2.5+2n)t cy C20 ns rd delay time from astb t astrd 0.5t cy C30 ns wr delay time from astb t astwr 1.5t cy C30 ns astb - delay time from t rdast t cy -10 t cy +40 ns rd - in external fetch address hold time from t rdadh t cy t cy +50 ns rd - in external fetch write data output time from rd - t rdwd 10 ns wr delay time from write data t wdwr v dd = 4.5 to 6.0 v 0.5t cy C120 0.5t cy ns 0.5t cy C170 0.5t cy ns address hold time from wr - t wradh v dd =4.5 to 6.0 v t cy t cy +60 ns t cy t cy +100 ns rd - delay time from wait - t wtrd 0.5t cy 2.5t cy +80 ns wr - delay time from wait - t wtwr 0.5t cy 2.5t cy +80 ns (2) read/write operation (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) remarks 1. t cy = t cy /4 2. n indicates number of waits. 3. c l = 100 pf (c l indicates load capacitance of p40/ad0 to p47/ad7, p50/a8 to p57/a15, p64/rd, p65/wr, p66/wait,p67/astb pins).
38 m pd78001b(a), 78002b(a) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy2 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high/low-level width t kh2 v dd = 4.5 to 6.0 v 400 ns t kl2 1600 ns si setup time (to sck - ) t sik2 100 ns si hold time (from sck - ) t ksi2 400 ns so output delay time from t kso2 c = 100 pf * v dd = 4.5 to 6.0 v 300 ns sck 1000 sck rise, fall time when external device expansion 160 ns function is used when external device expansion 1000 ns function is not used (3) serial interface (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) (a) 3-wire serial i/o mode (sck... internal clock output) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy1 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high/low-level width t kh1 v dd = 4.5 to 6.0 v t kcy1 /2-50 ns t kl1 t kcy1 /2-150 ns si setup time (to sck - ) t sik1 100 ns si hold time (from sck - ) t ksi1 400 ns so output delay time from t kso1 c = 100 pf * v dd = 4.5 to 6.0 v 300 ns sck 1000 ns * c is the load capacitance of so output line. (b) 3-wire serial i/o mode (sck... external clock input) t r2 t f2 * c is the load capacitance of so output line.
m pd78001b(a), 78002b(a) 39 parameter symbol test conditions min. typ. max. unit sck cycle time t kcy3 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high/low-level width t kh3 v dd = 4.5 to 6.0 v t kcy3 /2-50 ns t kl3 t kcy3 /2-150 ns sb0, sb1 setup time t sik3 v dd = 4.5 to 6.0 v 100 ns (to sck ) 300 ns sb0, sb1 hold time t ksi3 t kcy3 /2 ns from sck ? sb0, sb1 output delay time t kso3 r = 1 k w , v dd = 4.5 to 6.0 v 0 250 ns (from sck ) c = 100 pf * 0 1000 ns sb0, sb1 ? from sck t ksb t kcy3 ns sck ? from sb0, sb1 ? t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns (c) sbi mode (sck... internal clock output) * r and c are the load resistors and load capacitance of the sb0 and sb1 output line. parameter symbol test conditions min. typ. max. unit sck cycle time t kcy4 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high/low-level width t kh4 v dd = 4.5 to 6.0 v 400 ns t kl4 1600 ns sb0, sb1 setup time t sik4 v dd = 4.5 to 6.0 v 100 ns (to sck ) 300 ns sb0, sb1 hold time t ksi4 t kcy4/ 2ns (from sck ?) sb0, sb1 output delay time t kso4 r = 1 k w , v dd = 4.5 to 6.0 v 0 300 ns from sck c = 100 pf * 0 1000 ns sb0, sb1 ? from sck t ksb t kcy4 ns sck ? from sb0, sb1 ? t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck rise, fall time when external device expansion 160 ns function is used when external device expansion 1000 ns function is not used (d) sbi mode (sck... external clock input) * r and c are the load resistors and load capacitance of the sb0 and sb1 output line. t r4 t f4
40 m pd78001b(a), 78002b(a) (e) 2-wire serial i/o mode (sck... internal clock output) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy5 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-level width t kh5 r = 1 k w , c = 100 pf * t kcy5 /2-50 ns sck low-level width t kl5 t kcy5 /2-50 ns sb0, sb1 setup time t sik5 300 ns (to sck ) sb0, sb1 hold time t ksi5 600 ns (from sck ) sb0, sb1 output delay time t kso5 r = 1 k w , v dd = 4.5 to 6.0 v 0 250 ns from sck ? c = 100 pf * 0 1000 ns * r and c are the load resistors and load capacitance of the sck0, sb0 and sb1 output line. (f) 2-wire serial i/o mode (sck... external clock input) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy6 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-level width t kh6 650 ns sck low-level width t kl6 800 ns sb0, sb1 setup time t sik6 100 ns (to sck ) sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck ) sb0, sb1 output delay time t kso6 r = 1 k w , v dd = 4.5 to 6.0 v 0 300 ns from sck ? c = 100 pf * 0 1000 ns sck rise, fall time when external device expansion 160 ns function is used when external device expansion 1000 ns function is not used * r and c are the load resistors and load capacitance of the sck0, sb0 and sb1 output line. t r6 t f6
m pd78001b(a), 78002b(a) 41 ac timing test point (excluding x1, xt1 input) ti timing clock timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t xl t xh 1/f x v dd - 0.5 v 0.4v t xtl t xth 1/f xt v dd - 0.5 v 0.4v x1 input xt1 input t til t tih 1/f ti ti1, ti2
42 m pd78001b(a), 78002b(a) read/write operation external fetch (no wait): external fetch (wait insertion): t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8-a15 ad0-ad7 astb rd upper 8-bit address operation code lower 8-bit address t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8-a15 ad0-ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 upper 8-bit address operation code lower 8-bit address
m pd78001b(a), 78002b(a) 43 external data access (no wait): external data access (wait insertion): t rdwd t wdh t asth t adh t add2 hi-z t ads t astrd t rdl2 a8-a15 ad0-ad7 astb rd t wds t wrl1 wr t rdd2 t rdh hi-z t wdwr t astwr upper 8-bit address write data read data lower 8-bit address t wradh t astrd t asth t adh t add2 hi-z t ads t rdl2 a8-a15 ad0-ad7 astb rd t wds t wrl1 wr t rdh hi-z t wdwr t astwr t wradh upper 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd
44 m pd78001b(a), 78002b(a) serial transfer timing 3-wire serial i/o mode: sbi mode (command signal transfer): sbi mode (bus release signal transfer) : t kcy 1,2 t kl1,2 t kh1,2 sck si so t sik1,2 t ksi1,2 t kso1,2 input data output data t r2 t f2 t sik3,4 t kcy3,4 t kl3,4 t kh3,4 sck t ksb t sbk t ksi3,4 t kso3,4 sb0, sb1 t r4 t f4 t sik3,4 t kcy3,4 t kl3,4 t kh3,4 sck t sbl t sbh t ksb t sbk t ksi3,4 t kso3,4 sb0, sb1 t r4 t f4
m pd78001b(a), 78002b(a) 45 2-wire serial i/o mode: t kso5,6 t sik5,6 t kcy5,6 t kl5,6 t kh5,6 sck t ksi5,6 sb0, sb1 t r6 t f6
46 m pd78001b(a), 78002b(a) parameter symbol test conditions min. typ. max. unit data retention v dddr 2.0 6.0 v supply voltage data retention v dddr = 2.0 v supply i dddr subsystem clock stop and 0.1 10 m a current feed-back resister disconnected release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 18 /fx m s wait time release by interrupt * m s data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) * in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register, selection of 2 13 /fx and 2 15 /fx to 2 18 /fx is possible. data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) t srel t wait v dd reset stop instruction execution stop mode data retension mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retension mode halt mode operating mode standby release signal (interrupt request) v dddr
m pd78001b(a), 78002b(a) 47 interrupt input timing reset input timing t intl t inth t intl intp0-intp2 intp3 t rsl reset
48 m pd78001b(a), 78002b(a) 12. characteristic curve (reference values) i dd vs v dd (main system clock : 8.38 mhz) 0234 56 78 f x =8.38mhz f xt =32.768khz pcc=b0h pcc=00h pcc=01h pcc=02h pcc=03h pcc=04h halt pcc=30h (t a =25?) 10.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 supply voltage v dd [v] supply current i dd [ma] (x1 oscillation, xt1 oscillation) 0.001 halt stop (x1 stop, xt1 oscillation) (x1 stop, xt1 oscillation)
49 m pd78001b(a), 78002b(a) i dd vs v dd (main system clock : 4.19 mhz) 0234 56 78 f x =4.19mhz f xt =32.768khz pcc=b0h pcc=00h pcc=01h pcc=02h pcc=03h (t a =25?) 10.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 supply voltage v dd [v] supply current i dd [ma] halt (x1 oscillation, xt1 oscillation) pcc=04h pcc=30h 0.001 halt stop (x1 stop, xt1 oscillation) (x1 stop, xt1 oscillation)
50 m pd78001b(a), 78002b(a) i dd vs f x i dd vs f x pcc=00h pcc=01h pcc=02h pcc=03h pcc=04h halt (x1 oscilla- tion) (v dd = 3 v, t a = 25 ?) 5 4 3 2 1 01 23 45 67 89101112 clock oscillator frequency f x [mhz] supply current i dd [ma] 0 pcc=00h pcc=01h pcc=02h pcc=03h pcc=04h halt (x1 oscilla- tion) (v dd = 5 v, t a = 25 ?) 5 4 3 2 1 01 23 45 67 89101112 clock oscillator frequency f x [mhz] supply current i dd [ma] 10 9 8 7 6 12 11 0
51 m pd78001b(a), 78002b(a) v ol vs i ol (port 0, 2 to 5, p64 to p67) v ol vs i ol (p60 to p63) v oh vs i oh (port 0 to 5, p64 to p67) v ol vs i ol (port 1) 30 20 10 0 0 0.5 1.0 v dd =6 v v dd =5 v v dd =4 v v dd =3 v output voltage low v ol [v] output current low i ol [ma] (t a =25 ?) -10 -5 0 0 0.5 1.0 (t a =25 ?) v dd =6 v v dd =5 v v dd =4 v v dd =3 v output voltage high v dd ?v oh [v] output current high i oh [ma] 30 20 10 0 0 0.5 1.0 (t a =25 ?) v dd =6 v v dd =5 v v dd =4 v v dd =3 v output voltage low v ol [v] output current low i ol [ma] 30 20 10 0 0 0.5 1.0 (t a =25 ?) v dd = 6 v v dd =5 v v dd =4 v v dd =3 v output voltage low v ol [v] output current low i ol [ma]
52 m pd78001b(a), 78002b(a) 13. package drawings drawings of mass-production product packages (1/2) 64-pin plastic shrink dip (750 mil) a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15 +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 caution dimensions and materials of es products are different from those of mass-production products. refer to drawings of es product packages (1/2).
m pd78001b(a), 78002b(a) 53 drawings of mass-production product packages (2/2) 64-pin plastic qfp ( n n 14) n a m f b 48 49 32 k l 64 1 17 16 33 d c detail of lead end s q 55 p m i h j g p64gc-80-ab8-3 item millimeters inches a b c d f g h i j k l 17.6 0.4 14.0 0.2 1.0 0.35 0.10 0.15 14.0 0.2 0.693 0.016 0.039 0.039 0.006 0.031 (t.p.) 0.551 note m n 0.10 0.15 1.8 0.2 0.8 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.008 0.014 0.551 0.8 0.2 0.031 p 2.55 0.100 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 2.85 max. 0.112 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 caution dimensions and materials are different from those of mass-production products. refer to drawings of es product packages (2/2).
54 m pd78001b(a), 78002b(a) drawings of es product packages (1/2) 64 33 132 a m 0~15 l b f d g j i h 64pin ceramic shrink dip (seam weld) (750 mil) m n c k p64d-70-750a1 item millimeters inches a b c d f g h i j k l 58.16 max. 1.778 (t.p.) 0.46 0.05 0.8 min. 3.5 0.3 1.02 min. 3.14 1.521 max. 2.290 max. 0.031 min. 0.138 0.012 0.124 0.200 max. 0.060 max. notes m n 0.25 0.25 0.05 18.8 19.05 (t.p.) 5.08 max. 0.018 0.002 0.01 0.010 +0.002 ?.003 0.740 1) each lead centerline is located within 0.25 mm (0.01 inch) of its true position (t.p.) at maximum material condition. 0.750 (t.p.) 0.040 min. 0.070 (t.p.) 2) item "k" to center of leads when formed parallel.
m pd78001b(a), 78002b(a) 55 drawings of es product packages (2/2) 64 pin ceramic qfp (14 14) (for es) b a d c g f h j 48 33 q m 49 32 116 64 17 t u v k (bottom view) x64b-80a-1 item millimeters inches 22.0 0.4 14.0 14.0 22.0 0.4 1.0 1.0 0.32 0.8 (t.p.) 4.0 0.15 0.25 3.0 max. 0.55 1.0 1.2 0.866 0.016 0.551 0.551 0.866 0.016 0.039 0.039 0.013 0.031 (t.p.) 0.157 0.01 0.119 max. 0.022 0.039 0.047 a b c d f g h j k m q t u v +0.007 ?.006
56 m pd78001b(a), 78002b(a) 14. recommended soldering conditions the m pd78001b(a)/78002b(a) should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (iei-1207) . for soldering methods and conditions other than those recommended below, contact our sales personnel. table 14-1 surface mounting type soldering conditions m pd78001bgc(a)- -ab8 : 64-pin plastic qfp ( n n 14 mm) m pd78002bgc(a)- -ab8 : 64-pin plastic qfp ( n n 14 mm) table 14-2 insertion type soldering conditions caution wave soldering is only for the pins in order that jet solder can not contact with the chip directly. m pd78001bcw(a)- : 64-pin plastic shrink dip (750 mil) m pd78002bcw(a)- : 64-pin plastic shrink dip (750 mil) infrared reflow vps pin part heating package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: twice max. < points to note > (1) start the second reflow after the device temprature by the first reflow returns to normal. (2) flux washing by the water after the first reflow should be avoided. package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above) number of times: twice max. < points to note > (1) start the second reflow after the device temprature by the first reflow returns to normal. (2) flux washing by the water after the first reflow should be avoided. pin temperature: 300 c max., duration: 3 sec. max. (per device side) recommended condition symbol ir35-00-2 vp15-00-2 soldering conditions soldering method caution use of more than one soldering method should be avoided (except in the case of pin part heating). soldering method wave soldering (pin only) pin part heating soldering conditions solder bath temperature: 260 c max., duration: 10 sec. max. pin temperature: 300 c max., duration: 3 sec. max. (per pin)
m pd78001b(a), 78002b(a) 57 appendix a. deveropment tools the following development tools are available for system development using the m pd78001b(a), 78002b(a). language processing software ra78k/0 *1, 2, 3 78k/0 series common assembler package cc78k/0 *1, 2 , 3 78k/0 series common c compiler package df78002 *1, 2 , 3 m pd78002 subseries device file cc78k/0-l *1, 2, 3 78k/0 series common c compiler library source file prom programming tools pg-1500 prom programmer pa-78p014cw programmer adapter connected to pg-1500 pa-78p014gc pg-1500 controller *1, 2 pg-1500 control program debugging tools ie-78000-r 78k/0 series common in-circuit emulator ie-78000-r-bk 78k/0 series common break board ie-78014-r-em m pd78002/78014 subseries evaluation emulation board ep-78240cw-r emulation probe common to m pd78244 subseries ep-78240gc-r ev-9200gc-64 socket to be mounted on user system board created for the 64-pin plastic qfp sd78k/0 *1, 2 ie-78000-r screen debugger sm78k/0 *4, 5, 6 78k/0 series common system simulator df78002 *1, 2, 4, 5 m pd78002 subseries device file enbedded os mx78k/0 *1, 2, 3, 6 78k/0 series common enbedded os fuzzy inference development support system fe9000 *1 /fe9200 *5 fuzzy knowledge data creation tool ft9080 *1 /ft9085 *2 translator fi78k0 *1, 2 fuzzy inference module fd78k0 *1, 2 fuzzy inference debugger *1. pc-9800 series (ms-dos tm ) based. 2. ibm pc/at tm (pc dos tm ) based. 3. hp9000 series 300 tm , hp9000 series 700 tm (hp-ux tm ) based, sparcstation tm , (sun os tm ) based, ews-4800 series (ews-ux/v) based. 4. pc-9800 series (ms-dos + windows tm ) based.
58 m pd78001b(a), 78002b(a) 5. ibm pc/at (pc dos + windows) based. 6. under development. remarks 1. for development tools manufactured by a third party, see the "78k/0 series selection guide" (if- 1185) . 2. ra78k/0, cc78k/0, sd78k/0, and sm78k/0 are used in combination with df78002.
m pd78001b(a), 78002b(a) 59 development tools documents (user's manual) document name document no. (japanese) document no. (engligh) ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 pg-1500 prom programmer eeu-651 eeu-1335 pg-1500 controller eeu-704 eeu-1291 ie-78000-r eeu-810 eeu-1398 ie-78000-r-bk eeu-867 eeu-1427 ie-78014-r-em eeu-805 eeu-1400 ep-78240 eeu-986 in preparation sd78k/0 screen debugger beginner's guide eeu-852 eeu-1414 reference eeu-816 eeu-1413 appendix b. related documents device related documents document name document no. (japanese) document no. (engligh) user's manual ieu-788 ieu-1334 78k/0 series user's manual - instruction ieu-849 ieu-1372 application note basic i iea-715 iea-1288 basic ii iea-740 iea-1299 eeu-862 eeu-1444 embedded software documents (user's manual) document name document no. (japanese) document no. (engligh) fuzzy knowledge data creation tool eeu-892 eeu-1438 78k/0, 78k/ii, 87ad series fuzzy inference development support system - translator caution these documents above are subject to change without notice. besure to use the latest document for designing your system.
60 m pd78001b(a), 78002b(a) other documents document name document no. (japanese) document no. (engligh) package manual iei-635 iei-1213 semiconductor device mounting technology manual iei-616 iei-1207 quality grade on nec semiconductor devices iei-620 iei-1209 semiconductor device quality guarantee guide mei-603 mei-1202 caution these documents above are subject to change without notice. besure to use the latest document for designing your system.
m pd78001b(a), 78002b(a) 61 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immedi- ately after power-on for devices having reset function.
m pd78001b(a), 78002b(a) [memo] fip is a registered trademark of nec corporation. iebus is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re- export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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